Most digital to-analog converters (DACs) today are of the R-2R type. FIG. 1 shows a simplified circuit diagram of an eight bit R-2R ladder DAC of the prior art. The switches 1 through S8 are FET switches which are controlled by an eight bit digital input word to the DAC. Each bit position in the digital word controls a respective switch to send the current through the respective legs of the circuit (i.e., the 2R resistor above the switch) either to analog ground 12, if the corresponding bit is a 0, or to the summing junction 14, if the corresponding bit is a 1. S1 is controlled by the most significant bit of the digital word while each successive switch is controlled by the next most significant bit. The summing junction 14 is held at virtual ground by the output buffer amp 16. Due to the configuration of the resistors having impedances of R and 2R, the current in each leg is one half the current in the preceding (i.e., next most significant) leg. However, since there is no resistance R in series with the resistance 2R in leg 9, the current in legs 8 and 9 are egual.
Vref, the input voltage to the R-2R ladder, is a reference voltage which provides a current I into the ladder. The R-2R configuration will split the input current I between analog ground 12 and the summing junction 14 in accordance with the switches S1-S8 and the digital input word. The buffer amplifier 16 converts the current at the summing node 14 into a voltage, V.sub.out. V.sub.out is the analog output voltage corresponding to the digital input word.
As an example, if the digital input word is 10010010, the current flowing through legs 1, 4 and 7 would be directed to the summing node 14 while the current in legs 2, 3, 5, 6 and 8 would be sent to analog ground 12. If we call the current in leg 1 I.sub.msb, then the current at the summing junction 14 will be I.sub.msb +1/8 I.sub.msb +1/64 I.sub.msb. The remaining current, 1/2 I.sub.msb +1/4 I.sub.msb +1/6 I.sub.msb +1/32 I.sub.msb +1/128 I.sub.msb, is sent to analog ground. The buffer amplifier 16 converts the current at summing junction 14 to a voltage at V.sub.out. Since the buffer amplifier 16 is an inverting amplifier, V.sub.out will be a negative voltage if Vref is a positive voltage. In order to obtain a positive output voltage, the V.sub.out signal is inverted at a later stage in the signal processing of the DAC.
The R-2R ladder shown in FIG. 1 is configured to operate only in a uni-polar mode, that is, its output can only be of the opposite polarity of the applied Vref. In order to obtain four guadrant operation, i.e., allow for a positive or negative analog output voltage in response to a positive or negative digital input word using offset binary or two's-complement codes, an offset current equal and opposite to 1/2 Iref is added to the summing junction 14. This causes the voltage at V.sub.out to be offset by exactly 1/2 the full scale range of the DAC. Therefore, if V.sub.out in the uni-polar mode has a range of 0 to 5 volts, V.sub.out would have a full scale range of .+-.2.5 volts in the bi-polar mode. The offset reference current may be provided by a separate offset reference. More usually, it is derived from the DAC's basic Vref signal in order to minimize drift of the output zero with temperature.
Errors are introduced into the analog output of a DAC if the analog ground 12 seen by the R-2R ladder drifts from the true ground seen by the related circuit components (i.e., the chip ground pin connector). Ideally, the conductor which leads from the switch terminals to ground and the ground line itself are perfect conductors and offer no electrical resistance to the circuit. Unfortunately, however, the conductor in the DAC does provide a small but non-negligible resistance to the circuit. This resistance causes the voltage at the switch terminals to drift from true ground to some offset value, thereby offsetting all currents to both analog ground 12 and the summing junction 14 and causing inaccurate readings. Analog ground drift, as it is called, which is about 1/2 or more of the amplitude of the least significant bit (as determined by Vref and the number of bits of resolution) causes inaccurate operation of the DAC and is unacceptable. Unfortunately, errors of greater than 1/2 lsb are easily accumulated, particularly in monolithic chips carrying a multiplicity of DACs. In such chips, the total amount of conductor resistance between the pin which is to be connected to analog ground and the actual switches in the DAC can be quite significant and particularly bothersome in higher accuracy DACs.
For instance, a 12-bit DAC having a reference voltage of 10 volts would have a least significant bit value of 2.5 mV. An analog ground drift of more than 1.25 mV (1/2lsb) would cause an error in the analog output of the DAC. If the ground wire offers a resistance of 1 ohm to the circuit, then an analog ground current of just 1.25 mA would cause an unacceptable analog ground drift of 1.25 mV.
Another error introduced into the analog output in prior art DACs is caused by the temperature dependence of the FET switches used in the R 2R ladder as well as additional FET switches that might be included for such purposes a selecting uni polar or bi polar operation or selecting a full scale range for the DAC. The resistance offered to the circuit by the FET switches drifts with temperature, thereby causing the analog output also to drift with temperature. The amount by which the resistance of the FET switches drifts with temperature is defined by the "temperature coefficient", or TC, of the switch.
Therefore, it is an object of the present invention to provide a monolithic digital-to-analog converter that is substantially immune to analog output drift due to the TC of the FET switches in the circuitry.
It is a further object of the present invention to provide a monolithic digital-to-analog converter that substantially eliminates the effect of analog ground current on the output analog voltage.
It is yet another object of the present invention to provide a monolithic digital to-analog converter capable of being selectively programmed to operate in either uni-polar or bi-polar modes.
Additionally, it is a further object of the present invention to provide an improved monolithic digital-to-analog converter.